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3-194 hsp43220 decimating digital filter the hsp43220 decimating digital filter is a linear phase low pass decimation ?lter which is optimized for ?ltering narrow band signals in a broad spectrum of a signal processing applications. the hsp43220 offers a single chip solution to signal processing applications which have historically required several boards of ics. this reduction in component count results in faster development times as well as reduction of hardware costs. the hsp43220 is implemented as a two stage ?lter structure. as seen in the block diagram, the ?rst stage is a high order decimation ?lter (hdf) which utilizes an ef?cient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass ?ltering process. the hdf provides up to 96db aliasing rejection in the signal pass band. the second stage consists of a ?nite impulse response (fir) decimation ?lter structured as a transversal fir ?lter with up to 512 symmetric taps which can implement ?lters with sharp transition regions. the fir can perform further decimation by up to 16 if required while preserving the 96db aliasing attenuation obtained by the hdf. the combined total decimation capability is 16,384. the hsp43220 accepts 16-bit parallel data in 2s complement format at sampling rates up to 33 msps. it provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ics to a common bus. the hsp43220 also provides the capability to bypass either the hdf or the fir for additional ?exibility. features ? single chip narrow band filter with up to 96db attenuation ? dc to 33mhz clock rate ? 16-bit 2s complement input ? 20-bit coef?cients in fir ? 24-bit extended precision output ? programmable decimation up to a maximum of 16,384 ? standard 16-bit microprocessor interface ? filter design software available decimate? ? up to 512 taps applications ? very narrow band filters ? zoom spectral analysis ? channelized receivers ? large sample rate converter block diagram ordering information part number temp. range ( o c) package pkg. no. hsp43220vc-33 0 to 70 100 ld mqfp q100.14x20 HSP43220JC-15 0 to 70 84 ld plcc n84.1.15 hsp43220jc-25 0 to 0 84 ld plcc n84.1.15 hsp43220jc-33 0 to 70 84 ld plcc n84.1.15 hsp43220gc-25 0 to 70 84 ld cpga g84.a hsp43220gc-33 0 to 70 84 ld cpga g84.a decimate software development tool (this software tool may be downloaded from our internet site: http://www.intersil.com) input clock data input data out fir clock decimation up to 1024 decimation up to 16 data ready 24 control and coefficients 16 16 fir decimation filter high order decimation filter data sheet february 1999 file number 2486.7 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 decimate? is a trademark of intersil corporation.
3-195 pinouts 84 pin grid array (pga) hsp43220 bottom view pins up a b c d e f g h j k l 12 3456789 11 c _ bus 6 c _ bus 3 c _ bus 2 c _ bus 0 out _ enx v cc data _ rdy data _ out 23 data _ out 21 data _ out 20 data _ out 18 v cc c _ bus 1 c _ bus 4 c _ bus 5 c _ bus 8 gnd data _ out 22 data _ out 19 data _ out 17 data _ out 15 out_ selh fir _ ck gnd data _ out 14 data _ out 16 data_ out 12 data _ out 13 data _ out 10 data _ out 11 gnd data _ out 8 data _ out 9 v cc out _ enp data _ out 7 data _ out 6 data _ out 5 data _ out 4 data _ out 3 data _ out 2 data _ out 0 data_ out 1 v cc gnd gnd v cc in 4 data _ in 2 data _ in 1 data _ gnd in 3 data _ in 0 data _ start out start in a0 a1 reset cs wr v cc ast ar t in c _ bus 7 c _ bus 9 v cc c _ bus 10 c _ bus 15 c _ bus 14 c _ bus 13 c _ bus 11 c _ bus 12 in 7 data _ in 8 data _ in 11 data _ in 14 data _ in 6 data _ in 13 data _ in 12 data _ in 15 data _ ck_in gnd in 5 data _ in 9 data _ in 10 data _ 10 a b c d e f g h j k l 1 2345678 9 11 10 hsp43220 top view pins down c _ bus 6 c _ bus 3 c _ bus 2 c _ bus 0 out _ enx v cc data _ rdy data _ out 23 data _ out 21 data _ out 20 data _ out 18 v cc c _ bus 1 c _ bus 4 c _ bus 5 c _ bus 8 gnd data _ out 22 data _ out 19 data _ out 17 data _ out 15 out_ selh fir _ ck gnd data _ out 14 data _ out 16 data_ out 12 data _ out 13 data _ out 10 data _ out 11 gnd data _ out 8 data _ out 9 v cc out _ enp data _ out 7 data _ out 6 data _ out 5 data _ out 4 data _ out 3 data _ out 2 data _ out 0 data_ out 1 v cc gnd gnd v cc in 4 data _ in 2 data _ in 1 data _ in 3 data _ in 0 data _ st ar t out st ar t in a0 a1 reset cs wr v cc ast ar t in c _ bus 7 c _ bus 9 v cc c _ bus 10 c _ bus 15 c _ bus 14 c _ bus 13 c _ bus 11 c _ bus 12 in 7 data _ in 8 data _ in 11 data _ in 14 data _ in 6 data _ in 13 data _ in 12 data _ in 15 data _ ck_in gnd in 5 data _ in 9 data _ in 10 data _ gnd hsp43220
3-196 100 lead mqfp top view pinouts (continued) data_out14 data_out15 dout_out16 data_out17 data_out19 data_out20 data_out18 data_out13 data_out7 data_out8 data_out9 data_out10 gnd gnd v cc v cc data_out12 data_out11 data_out6 v cc v cc gnd gnd data_out1 data_out2 data_out3 data_out4 data_out5 data_out0 ck_in 99 98 97 96 95 94 93 91 89 87 85 84 83 81 82 86 88 90 92 100 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 40 42 44 46 47 48 50 49 45 43 41 39 31 v cc gnd gnd v cc data_in15 data_in14 data_in13 data_in12 data_in11 data_in10 data_in9 data_in8 data_in7 data_in6 data_in5 data_in4 data_in0 data_in3 data_in2 data_in1 c_bus11 cs c_bus15 c_bus14 c_bus13 c_bus12 c_bus10 c_bus9 v cc v cc wr gnd c_bus8 gnd gnd nc st ar t out v cc v cc ast ar tin st ar tin reset a1 a0 gnd c_bus7 c_bus6 c_bus4 nc c_bus5 gnd v cc gnd v cc c_bus3 data_out21 gnd v cc gnd v cc c_bus2 c_bus1 c_bus0 out_selh out_ enp out_ enx fir_ck d a t a_ rd y data_out23 data_out22 hsp43220
3-197 84 plastic leaded chip carrier (plcc) pin description name type description v cc the +5v power supply pins. gnd the device ground. ck_in i input sample clock. operations in the hdf are synchronous with the rising edge of this clock signal. the maximum clock frequency is 33mhz. ck_in is synchronous with fir_ck and thus the two clocks may be tied together if required, or ck_in can be divided down from fir_ck. ck_in is a cmos level signal. fir_ck i input clock for the fir filter. this clock must be synchronous with ck_in. operations in the fir are synchronous with the rising edge of this clock signal. the maximum clock frequency is 33mhz. fir_ck is a cmos level signal. data_in0-15 i input data bus. this bus is used to provide the 16-bit input data to the hsp43220. the data must be provided in a synchro- nous fashion, and is latched on the rising edge of the ck_in signal. the data bus is in 2's complement fractional format. bit 15 is the msb. c_bus0-15 i control input bus. this input bus is used to load all the ?lter parameters. the pins wr, cs and a0, a1 are used to select the destination of the data on the control bus and write the control bus data into the appropriate register as selected by a0 and a1 data_out 0-23 o output data bus. this 24-bit output port is used to provide the ?ltered result in 2's complement format. the upper 8 bits of the output, data_out16-23 will provide extension or growth bits depending on the state of out_selh and whether the fir has been put in bypass mode. output bits data_out0-15 will provide bits 20 through 2-15 when the fir is not by- passed and will provide the bits 2-16 through 2-31 when the fir is in bypass mode. data_rdy o an active high output strobe that is synchronous with fir_ck that indicates that the result of the just completed fir cycle is available on the data bus. reset i reset is an asynchronous signal which requires that the input clocks ck_in and fir_ck are active when reset is as- serted. reset disables the clock divider and clears all of the internal data registers in the hdf. the fir ?lter data path is not initialized. the control register bits that are cleared are f_byp, h_stages, and h_drate. the f_dis bit is set. in order to guarantee consistent operation of the part, the user must reset the ddf after power up. wr i write strobe. wr is used for loading the internal registers of the hsp43220. when cs and wr are asserted, the rising edge of wr will latch the c_bus0-15 data into the register specified by a0 and a1. cs i chip select. the chip select input enables loading of the internal registers. when cs and wr are low, the a0 and a1 address lines are decoded to determine the destination of the data on c_bus0-15. the rising edge of wr then loads the appropriate register as specified by a0 and a1. pinouts (continued) 111098765432184838281807978777675 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 data_in 1 data_in 0 v cc gnd ck_in v cc gnd data_in 2 data_in 3 data_in 4 data_in 5 data_in 6 data_in 7 data_in 8 data_in 9 data_in 10 data_in 11 data_in 12 data_in 13 data_in 14 data_in 15 data_out 1 data_out 0 gnd data_out 2 data_out 3 data_out 4 data_out 5 data_out 6 data_out 7 data_out 8 data_out 9 data_out 10 data_out 11 gnd v cc data_out 12 data_out 13 data_out 14 data_out 15 data_out 16 data_out 17 a0 c_bus 15 a1 v cc v cc gnd st ar t out wr cs c_bus 14 c_bus 13 c_bus 12 c_bus 11 c_bus 10 c_bus 9 c_bus 8 c_bus 7 c_bus 6 st ar tin c_bus 5 c_bus 4 c_bus 3 c_bus 2 c_bus 1 c_bus 0 v cc out_selh out_enp out_enx gnd data_rdy fir_ck v cc gnd data_out 23 data_out 22 data_out 21 data_out 20 data_out 19 data_out 18 reset ast ar tin hsp43220
3-198 the hdf the first filter section is called the high order decimation filter (hdf) and is optimized to perform decimation by large factors. it implements a low pass filter using only adders and delay elements instead of a large number of multiplier/ accumulators that would be required using a standard fir filter. the hdf is divided into 4 sections: the hdf ?lter section, the clock divider, the control register logic and the start logic (figure 1). data shifter after being latched into the input register the data enters the data shifter. the data is positioned at the output of the shifter to prevent errors due to overflow occurring at the output of the hdf. the number of bits to shift is controlled by h_growth. integrator section the data from the shifter goes to the integrator section. this is a cascade of 5 integrator (or accumulator) stages, which implement a low pass filter. each accumulator is implemented as an adder followed by a register in the feed forward path. the integrator is clocked by the sample clock, ck_in as shown in figure 2. the bit width of each integrator stage goes from 66 bits at the ?rst integrator down to 26 bits at the output of the ?fth integrator. bit truncation is performed at each integrator stage because the data in the integrator stages is being accumulated and thus is growing, therefore the lower bits become insigni?cant, and can be truncated without losing signi?cant data. a0, a1 i control register address. these lines are decoded to determine which control register is the destination for the data on c_bus0-15. register loading is controlled by the a0 and a1, wr and cs inputs. ast ar tin i ast ar tin is an asynchronous signal which is sampled on the rising edge of ck_in. it is used to put the ddf in operational mode. ast ar tin is internally synchronized to ck_in and is used to generate st ar t out. st ar t out o st ar t out is a pulse generated from the internally synchronized version of ast ar tin. it is provided as an output for use in multi-chip con?gurations to synchronously start multiple hsp43220's. the width of st ar t out is equal to the period of ck_in. st ar tin i st ar tin is a synchronous input. a high to low transition of this signal is required to start the part. st ar tin is sampled on the rising edge of ck_in. this synchronous signal can be used to start single or multiple hsp43220's. out_selh i output select. the out_selh input controls which bits are provided at output pins data_out16-23. a high on this control line selects bits 28 through 21 from the accumulator output. a low on this control line selects bits 2-16 through 2-23 from the accumulator output. processing is not interrupted by this pin. out_ enp i output enable. the out_enp input controls the state of the lower 16 bits of the output data bus, data_out0-15. a low on this control line enables the lower 16 bits of the output bus. when out_enp is high, the output drivers are in the high imped- ance state. processing is not interrupted by this pin. out_ enx i output enable. the out_ enx input controls the state of the upper 8 bits of the output data bus, data_out16-23. a low on this control line enables the upper 8 bits of the output bus. when out_ enx is high, the output drivers are in the high impedance state. processing is not interrupted by this pin. pin description (continued) name type description figure 1. high order decimation filter figure hdf filter section dec reg integrator input reg comb filter round reg 26 16 to fir 16 19 26 66 16 16 istart comb_en1-5 h_growth int_en1-5 reset reset 5 ck_in ck_dec to fir st ar tin st ar t out start logic reset ast ar tin ck_in data in istart reset h_drate h_byp ck_in clock divider control register logic a0-1 wr cs c_bus comb_en1-5 655 h_growth int_en1-5 ck dec 5 6 data shifter hsp43220
3-199 there are three signals that control the integrator section; they are h_stages, h_byp and reset. in figure 2 these control signals have been decoded and are labelled int_en1 - int_en5. the order of the ?lter is loaded via the control bus and is called h_stages. h_stages is decoded to provide the enables for each integrator stage. when a given integrator stage is selected, the feedback path is enabled and the integrator accumulates the current data sample with the previous sum. the integrator section can be put in bypass mode by the h_byp bit. when h_byp or reset is asserted, the feedback paths in all integrator stages are cleared. decimation register the output of the integrator section is latched into the decimation register by ck_dec. the output of the decimation register is cleared when reset is asserted. the hdf decimation rate = h_drate +1, which is de?ned as h dec for convenience. comb filter section the output of the decimation register is passed to the comb filter section. the comb section consists of 5 cascaded comb filters or differentiators. each comb filter section calculates the difference between the current and previous integrator output. each comb filter consists of a register which is clocked by ck_dec, followed by an subtractor, where the subtractor calculates the difference between the input and output of the register. bit truncations are done at each stage as shown in figure 3. the first stage bit width is 26 bits and the output of the fifth stage is 19 bits. there are three signals that control the comb filter; h_ stages, h_byp and reset. in figure 3 these control signals are decoded as comb_en1 - comb_en5. the order of the comb ?lter is controlled by h_stages, which is programmed over the control bus. h_byp is used to put the comb section in bypass mode. reset causes the register output in each comb stage to be cleared. the h_ byp and reset control pins, when asserted force the output of all registers to zero so data is passed through the subtractor unaltered. when the h_stages control bits enable a given stage the output of the register is subtracted from the input. it is important to note that the comb filter section has a speed limitation. the input sampling rate divided by the decimation factor in the hdf (ck_in/h dec ) should not exceed 4mhz. violating this condition causes the output of the filter to be incorrect. when the hdf is put in bypass mode this limitation does not apply. equation 1 describes the relationship between f_taps, f_drate, h_drate, ck_in and fir_ck. rounder the ?lter accuracy is limited by the 16-bit data input. to maintain the maximum accuracy, the output of the comb is rounded to 16 bits. the rounder performs a symmetric round of the 19-bit output of the last comb stage. symmetric rounding is done to prevent the synthesis of a 0hz spectral component by the rounding process and thus causing a reduction in spurious free dynamic range. saturation logic is also provided to prevent roll over from the largest positive value to the most negative value after rounding. the output of the last comb ?lter stage in the hdf section has a 16-bit integer portion with a 3-bit fractional part in 2's complement format. figure 2. integrator mux int_en5 reg 66 63 0 mux int_en4 reg 53 0 mux int_en3 reg 43 0 mux int_en2 reg 35 0 mux int_en1 reg 26 0 from shifter to decimation register ck in ? ? ? ? ? figure 3. comb filter b a a-b comb_en5 reset reg b a a-b comb_en4 22 b a a-b comb_en3 21 b a a-b comb_en2 20 b a a-b comb_en1 19 deci- mation register 26 19 to rounder ck_dec reset reg reset reg reset reg reset reg from hsp43220
3-200 the rounding algorithm is as follows: the output of the rounder is latched into the hdf output register with ck_dec. ck_dec is generated by the clock divider section. the output of the register is cleared when reset is asserted. clock divider and control logic the clock divider divides ck_in by the decimation factor h dec to produce ck_dec. ck_dec clocks the decimation register, comb filter section, hdf output register. in the fir ?lter ck_dec is used to indicate that a new data sample is available for processing. the clock generator is cleared by reset and is not enabled until the ddf is started by an internal start signal (see start logic). the control register logic enables the updating of the control registers which contain all of the filter parameter data. when wr and cs are asserted, the control register addressed by bits a0 and a1 is loaded with the data on the c_bus. positive numbers fractional portion greater than or equal to 0.5 round up fractional portion less than 0.5 truncate negative numbers fractional portion less than or equal to 0.5 round up fractional portion greater than 0.5 truncate ddf control registers f_register (a1 = 0, a0 = 0) figure 4. f_oad f_byp f_esym f_drate f_taps fa0 fb0 es0 d3 d2 d1 d0 t8 t7 t6 t5 t4 t3 t2 t1 t0 f_taps bits t0-t8 are used to specify the number of fir ?lter taps. the number entered is one less than the number of taps required. for example, to specify a 511 tap ?lter f_taps would be programmed to 510. the mini- mum number of fir taps = 3 (f_taps = 2). f_drate bits d0-d3 are used to specify the amount of fir decimation. the num- ber entered is one less than the decimation required. for example, to specify decimation of 16, f_drate would be programmed to 15. for no fir decimation, f_drate would be set equal to 0. fdrate +1 is de?ned as f dec . f_esym bit es0 is used to select the fir symmetry. f_esym is set equal to one to select even symmetry and set equal to zero to select odd symmetry. when f_esym is one, data is added in the pre-adder; when it is zero, data is subtracted. normally set to one. f_byp fb0 is used to select fir bypass mode. fir bypass mode is selected by setting f_byp = 1. when fir bypass mode is selected, the fir is inter- nally set up for a 3 tap even symmetric filter, no decimation (f_drate = 0) and f_oad is set equal to one to zero one side of the preadder. in fir bypass mode all fir filter parameters, except f_cla, are ignored, includ- ing the contents of the fir coefficient ram. in fir bypass mode the out- put data is brought output on the lower 16 bits of the output bus data_out 0-15. to disable fir bypass mode, f_byp is set equal to zero. when f_byp is returned to zero, the coefficients must be reloaded. f_oad bit fa0 is used to select the zero the preadder mode. this mode zeros one of the inputs to the pre-adder. zero preadder mode is selected by setting f_oad equal to one. this feature is useful when implementing arbitrary phase ?lters or can be used to verify the ?lter coef?cients. to disable the zero preadder mode f_oad is set equal to zero. 15 14 13 1211109 87654321 0 hsp43220
3-201 fc_register (a1 = 0, a0 = 1) figure 5. h_register 1 (a1 = 1, a0 = 0) figure 6. ddf control registers (continued) f_cf c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 xxxxxxxxxxxxc3c2c1c0 f_cf bits c0-c19 represent the coefficient data, where c19 is the msb. two writes are required to write each coefficient which is 2's complement fractional format. the first write loads c19 through c4; c3 through c0 are loaded on the second write cycle. as the coefficients are written into this register they are formatted into a 20-bit coefficient and written into the coefficient ram sequentially starting with address location zero. the coefficients must be loaded sequentially, with the center tap being the last coeffi- cient to be loaded. see coefficient ram, below. 151413121110987654321 0 reserved f_dis f_cla h_byp h_drate fd0 fc0 hb0 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 151413 12 11 10 987654321 0 h_drate bits r0-r9 are used to select the amount of decimation in the hdf. the amount of deci- mation selected is programmed as the required decimation minus one; for instance to select decimation of 1024 h_drate is set equal to 1023. hdrate +1 is de?ned as h dec . h_byp bit hb0 is used to select hdf bypass mode. this mode is selected by setting h_byp = 1. when this mode is selected the input data passes through the hdf unfiltered. inter- nally h_stages and h_drate are both set to zero and h_growth is set to 50. h_register 2 must be reloaded when h_byp is returned to 0. to disable hdf bypass mode h_byp = 0. the relationship between ck_in and fir_ck in this and all other modes is defined by equation 1. f_cla bit fc0 is used to select the clear accumulator mode in the fir. this mode is enabled by setting f_cla = 1 and is disabled by setting f_cla = 0. in normal operation this bit should be set equal to zero. this mode zeros the feedback path in the accumulator of the multiplier/accumulator (mac). it also allows the multiplier output to be clocked off the chip by fir_ck, thus data_rdy has no meaning in this mode. this mode can be used in conjunction with the f_oad bit to read out the fir coefficients from the coeffi- cient ram. f_dis bit fd0 is used to select the fir disable mode. this feature enables the fir parame- ters to be changed. this feature is selected by setting f_dis = 1. this mode termi- nates the current fir cycle. while this feature is selected, the hdf continues to process data and write it into the fir data ram. when the fir re-programming is completed, the fir can be re-enabled either by clearing f_dis, or by asserting one of the start inputs, which automatically clears f_dis. hsp43220
3-202 start logic the start logic generates a start signal that is used internally to synchronously start the ddf. if ast ar tin is asserted ( st ar tin must be tied high) the start logic synchronizes it to ck_in by double latching the signal and generating the signal st ar t out, which is shown in figure 8. the st ar t out signal is then used to synchronously start other ddfs in a multi-chip con?guration (the st ar t out signal of the ?rst ddf would be tied to the st ar tin of the second ddf). the nand gate shown in figure 8 then passes this synchronized signal to be used on chip to provide a synchronous start. once started, the chip requires a reset to halt operation. when st ar tin is asserted ( ast ar tin must be tied high) the nand gate passes st ar tin which is used to provide the internal start, istart, for the ddf. when reset is asserted the internal start signal is held inactive, thus it is necessary to assert either ast ar tin or st ar tin in order to start the ddf. the timing of the first valid data_in with respect to st ar t_ in is shown in the timing waveforms. in using ast ar tin or st ar tin a high to low transition must be detected by the rising edge of ck_in, therefore these signals must have been high for more than one ck_in cycle and then taken low. the fir section the second ?lter in the top level block diagram is a finite impulse response (fir) ?lter which performs the ?nal shaping of the signal spectrum and suppresses the aliasing components in the transition band of the hdf. this enables the ddf to implement ?lters with narrow pass bands and sharp transition bands. the fir is implemented in a transversal structure using a single multiplier/accumulator (mac) and ram for storage of the data and filter coefficients as shown in figure 9. the fir can implement up to 512 symmetric taps and decimation up to 16. the fir is divided into 2 sections: the fir ?lter section and the fir control logic. coef?cient ram the coefficient ram stores the coefficients for the current fir filter being implemented. the coefficients are loaded into the coefficient ram over the control bus (c_bus). the coefficients are written into the coefficient ram sequentially, starting at location zero. it is only necessary to write one half of the coefficients when symmetric filters are being implemented, where the last coefficient to be written in is the center tap. h_register 2 (a1 = 1, a0 = 1) figure 7. ddf control registers (continued) reserved h_growth h_stages g5 g4 g3 g2 g1 g0 n2 n1 n0 h_stages bits n0-n2 are used to select the number of stages or order of the hdf ?lter. the number that is programmed in is equal to the required number of stages. for a 5th order ?lter, h_stages would be set equal to 5. h_growth bits g0-g5 are used to select the proper amount of growth bits. h_growth is calculated using the following equation: h_growth = 50 - ceiling {h_stages x log (h dec )/ log(2)} where the ceiling { } means use the next largest integer of the result of the value in brackets and log is the log to the base 10. the value of h_growth represents the position of the lsb on the output of the data shifter. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 figure 8. start logic ck_in reset istart st ar tin st ar t out ast ar tin s dq s dq hsp43220
3-203 the coef?cients are loaded into address 01 in two writes. the ?rst write loads the upper 16 bits of the 20-bit coef?cient, c4 through c19. the second write loads the lower 4 bits of the coef?cient, c0 through c3, where c19 is the msb. the two 16-bit writes are then formatted into the 20-bit coef?cient that is then loaded into the coef?cient ram starting at ram address location zero, where the coef?cient at this location is the outer tap (or the ?rst coef?cient value). to reload coef?cients, the coef?cient ram address pointer must be reset to location zero so that the coef?cients will be loaded in the order the fir ?lter expects. there are two methods that can be used to reset the coef?cient ram address pointer. the ?rst is to assert reset, which automatically resets the pointer, but also clears the hdf and alters some of the control register bits. ( reset does not change any of the coef?cient values.) the second method is to set the f_dis bit in control register h_ register1. this control bit allows any of the fir control register bits to be re- programmed, but does not automatically modify any control registers. when the programming is completed, the fir is re-started by clearing the f_dis bit or by asserting one of the start inputs ( ast ar tin or st ar tin). the f_dis bit allows the ?lter parameters to be changed more quickly and is thus the recommended reprogramming method. data ram the data ram stores the data needed for the ?lter calculation. the format of the data is: 2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 where the sign bit is in the 2 0 location. the 16-bit output of the hdf output register is written into the data ram on the rising edge of ck_dec. reset initializes the write pointer to the data ram. after a reset occurs, the output of the fir will not be valid until the number of new data samples written to the data ram equals taps. the ?lter always operates on the most current sample and the taps-1 previous samples. thus if the f_dis bit is set, data continues to be written into the data ram coming from the hdf section. when the fir is enabled again the ?lter will be operating on the most current data samples and thus another transient response will not occur. the maximum throughput of the fir ?lter is limited by the use of a single multiplier/accumulator (mac). the data output from the hdf being clocked into the fir ?lter by ck_dec must not be at a rate that causes an erroneous result being calculated because data is being overwritten. the equation shown below describes the relationship between, fir_ck, ck_dec, the number of taps that can be implemented in the fir, the decimation rate in the hdf and the decimation rate in the fir. (in the design considerations section of the operational section there is a chart that shows the tradeoffs between these parameters.) this equation expresses the minimum fir_ck. the minimum fir_ck is the smallest integer multiple of ck_in that satis?es equation 1. in addition, the tsk speci?cation must be met (see ac electrical speci?cations). f dec is the decimation rate in the fir (f dec = f_drate +1), where taps = the number of taps in the fir for even length ?lters and equals the number of taps+1 for odd length ?lters. solving the above equation for the maximum number of taps: in using this equation, it must be kept in mind that ck_in/ h dec must be less than or equal to 4mhz (unless the hdf is in bypass mode in which case this limitation in the hdf does not apply). in the operational section under the design considerations, there is a table that shows the trade- offs of these parameters. in addition, intersil provides a software package called decimate? which designs the ddf ?lter from system speci?cations. the registered outputs of the data ram are added or subtracted in the 17-bit pre-adder. the f_oad control bit allows zeros to be input into one side of the pre-adder. this provides the capability to implement non-symmetric ?lters. the selection of adding the register outputs for an even symmetric ?lter or for subtracting the register outputs for odd symmetric ?lter is provided by the control bit f_esym, which is programmed over the control bus. when subtraction is selected, the new data is subtracted from the old data. the 17-bit output of the adder forms one input of the multiplier/accumulator. a control bit f_cla provides the capability to clear the feedback path in the accumulator such that multiplier output will not be accumulated, but will instead ?ow directly to the output register. the bit weightings of the data and coef?cients as they are processed in the fir is shown below. input data (from hdf) 2 0 .2 -1 . . . 2 -15 pre-adder output 2 1 2 0 .2 -1 . . . 2 -15 coef?cient 2 0 .2 -1 . . . 2 -19 accumulator 2 8 . . . 2 0 .2 1 . . . 2 -34 fir output the 40 most signi?cant bits of the accumulator are latched into the output register. the lower 3 bits are not brought to the output. the 40 bits out of the output register are selected to be output by a pair of multiplexers. this register is clocked by fir_ck (see figure 9). fir_ck ck_in taps/2 () 4f dec ++ [] h dec f dec --------------------------------------------------------------------------------- - 3 (eq. 1) taps 2 fir_ck h dec f dec ck_in --------------------------------------------------------- - f dec -4 C ? ?? = (eq. 2) hsp43220
3-204 there are two multiplexers that route 24 of the 40 output bits from the output register to the output pins. the ?rst multiplexer selects the output register bits that will be routed to output pins data_out16-23 and the second multiplexer selects the output register bits that will be routed to output pins data_out0-15. the multiplexers are controlled by the control signal f_byp and the out_selh pin. f_byp and out_selh both control the first multiplexer that selects the upper 8 bits of the output bus, data_out16-23. f_byp controls the second multiplexer that selects the lower 16 bits of the output bus, data_out0-15. the output formatter is shown in detail in figure 10. fir control logic the data_rdy strobe indicates that new data is available on the output of the fir. the rising edge of data_rdy can be used to load the output data into an external register or ram. data format the ddf maintains 16 bits of accuracy in both the hdf and fir ?lter stages. the data formats and bit weightings are shown in figure 11. figure 9. fir filter reg reg reg reg reg pre-adder 16 f_esym f_oad 16 17 16 16 17 pre-adder logic 20 20 17 17 x 20 bit multiplier array reg 43-bit accumulator 37 37 43 43 f_cla multiplier/ accumulator section from hdf from coefficient formatter 16 20 16 x 512 data ram 20 x 256 coefficient ram output formatter output reg mux 40 f_cla data_rdy fir_ck data_out 0 -23 reg fir_ck data_rdy from control registers f_drate f_taps f_byp f_dis fir control logic 24 figure 10. fir output formatter out_selh 16 data_out0 -15 16 16 f_byp out_ enp f_byp = 1 2 -16 - 2 -31 f_byp = 0 40 mux 2 0 - 2 -15 8 data_out16-23 8 8 f_byp out_ enx f_byp = 0 2 8 - 2 1 f_byp = 0 mux 2 -16 - 2 -23 out_selh = 0 or f_byp = 1 out_selh = 1 hsp43220
3-205 operational section start con?gurations the scenario to put the ddf into operational mode is: reset the ddf by asserting the reset input, con?gure the ddf over the control bus, and apply a start signal, either by ast ar tin or st ar tin. until the ddf is put in operational mode with a start pulse, the ddf ignores all data inputs. to use the asynchronous start, an asynchronous active low pulse is applied to the ast ar tin input. ast ar tin is internally synchronized to the sample clock, ck_in, and generates st ar t out. this signal is also used internally when the asynchronous mode is selected. it puts the ddf in operational mode and allows the ddf to begin accepting data. when the ast ar tin input is being used, the st ar tin input must be tied high to ensure proper operation. to start the ddf synchronously, the st ar tin is asserted with a active low pulse that has been externally synchronized to ck_in. internally the ddf then uses this start pulse to put the ddf in operate mode and start accepting data inputs. when st ar tin is used to start the ddf the ast ar tin input must be tied high to prevent false starts. multi-chip start con?gurations since there are two methods to start up the ddf, there are also two configurations that can be used to start up multiple chips. the ?rst method is shown in figure 12. the timing of the st ar t out circuitry starts the second ddf on the same clock as the ?rst. if more ddfs are also to be started synchronously, st ar t out is connected to their st ar tin's. the second method to start up ddfs in a multiple chip con?guration is to use the synchronous start scenario. the startin input is wired to all the chips in the chain, and is asserted by a active low synchronous pulse that has been externally synchronized to ck_in. in this way all ddfs are synchronously started. the astartin input on all the chips is tied high to prevent false starts. the startout outputs are all left unconnected. this configuration is illustrated in figure 13. input data format fractional two's complement input 1514131211109876543210 -2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 fir coefficient format fractional two's complement input 19181716151413121110987654 3210 -2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 output data format fractional two's complement output for: out_selh = 1, f_byp = 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 for: out_selh = 0, f_byp = 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 -2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 for: out_selh = x, f_byp = 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 2 -25 2 -26 2 -27 2 -28 2 -29 2 -30 2 -31 figure 11. hsp43220
3-206 chip set application the hsp43220 is ideally suited for narrow band ?ltering in communications, instrumentation and signal processing applications. the hsp43220 provides a fully integrated solution to high order decimation ?ltering. the combination of the hsp43220 and the hsp45116 (which is a ncom numerically controlled oscillator / modulator) provides a complete solution to digital receivers. the diagram in figure 14 illustrates this concept. the hsp45116 down converts the signal of interest to baseband, generating a real component and an imaginary component. a hsp43220 then performs low pass ?ltering and reduces the sampling rate of each of the signals. the system scenario for the use of the ddf involves a narrow band signal that has been over-sampled. the signal is over-sampled in order to capture a wide frequency band containing many narrow band signals. the ncom is tuned to the frequency of the signal of interest and performs a complex down conversion to baseband of this signal, which results in a complex signal centered at baseband. a pair of ddfs then low pass ?lters the ncom output, extracting the signal of interest. design trade-off considerations equation 2 in the functional description section expresses the relationship between the number of taps which can be implemented in the fir as a function of ck_in, fir_ck, h dec , f dec . table 1 provides a tradeoff of these parameters. for a given speed grade and the ratio of the clocks, and assuming minimum decimation in the hdf, the number of fir taps that can be implemented is given in equation 2. figure 12. asynchronous start up figure 13. synchronous start up ddf ast ar tin st ar tin st ar t out ddf ast ar tin st ar t out ck_in fir_ck +5v nc st ar tin +5v to other ddf's ck_in fir_ck ddf ast ar tin st ar tin st ar t out ddf ast ar tin st ar t out +5v +5v st ar tin nc ck_in fir_ck ck_in fir_ck figure 14. digital channelizer cos (wt) sin (wt) hsp43220 ddf hsp43220 ddf sampled input data 0 10mhz 0 20mhz 0 hsp45116 ncom hsp43220
3-207 decimate intersil provides a development system which assists the design engineer to utilizing this ?lter. the decimate software package provides the user with both ?lter design and simulation environments for ?lter evaluation and design. these tools are integrated within one standard dsp cad environment, the athena group's monarch professional dsp software package. the software package is designed speci?cally for the ddf. it provides all the ?lter design software for this proprietary architecture. it provides a user-friendly menu driven interface to allow the user to input system level ?lter requirements. it provides the frequency response curves and a data ?ow simulation of the speci?ed ?lter design (figure 15). it also creates all the information necessary to program the ddf, including a prom ?le for programming the control registers. this software package runs on an ibm? pc?, xt?, at?, ps/2? computer or 100% compatible with the following con?guration: 640k ram 5.25 or 3.5 floppy drive hard disk math co-processor ms/pc-dos 2.0 or higher cga, mcga, ega, vga and hercules graphics adapters for more information, see the description of decimate in the development tools section of this data book. table 1. design trade off for minimum h dec speed grade (mhz) fir_ck ck_in min h dec taps f dec = 1 f dec = 2 f dec = 4 f dec = 8 f dec = 16 33 1 9 8 24 56 120 248 25.6 1 7 4 16 40 88 184 15 1 4 (note) 4 16 40 88 33 2 5 10 28 64 136 280 25.6 2 4 6 20 48 104 216 15 2 2 (note) 4 16 40 88 33 4 3 14 36 80 168 344 25.6 4 2 6 20 48 104 216 15 4 1 (note) 4 16 40 88 33 8 2 22 52 112 232 472 25.6 8 1 6 20 48 104 216 15 8 1 6 20 48 104 216 note: filter not realizable. hsp43220
3-208 figure 15. decimate design module screens hsp43220
3-209 absolute maximum ratings t a =25 o c thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied . . . . .gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) cpga package . . . . . . . . . . . . . . . . . . 35 5 mqfp package . . . . . . . . . . . . . . . . . . 33 n/a plcc package. . . . . . . . . . . . . . . . . . . 35 n/a maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature cpga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c mqfp and plcc package . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (mqfp, plcc - lead tips only) die characteristics component count . . . . . . . . . . . . . . . . . . . . . . . 193,000 transistors caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v high level clock input v ihc v cc = 5.25v 3.0 - v low level clock input v ilc v cc = 4.75v - 0.8 v output high voltage v oh i oh = -400 m a, v cc = 4.75v 2.6 - v output low voltage v ol i ol = +2.0ma, v cc = 4.75v - 0.4 v input leakage current i i v in = v cc or gnd, v cc = 5.25v -10 10 m a i/o leakage current i o v out = v cc or gnd, v cc = 5.25v -10 10 m a standby power supply current i ccsb v in = v cc or gnd v cc = 5.25v, note 3 - 500 m a operating power supply current i ccop f = 15mhz, v in = v cc or gnd, v cc = 5.25v, notes 2 and 4 - 120 ma capacitance t a = 25 o c, note 3 parameter symbol test conditions min max units input capacitance c in freq = 1mhz, v cc = open, all measurements are referenced to device ground -12pf output capacitance c o -10pf notes: 2. power supply current is proportional to operating frequency. typical rating for i ccop is 8ma/mhz. 3. not tested, but characterized at initial design and at major process/design changes. 4. output load per test load circuit with switch open and c l = 40pf. hsp43220
3-210 ac electrical speci?cations v cc = +4.75v to +5.25v, t a = 0 o c to 70 o c parameter symbol notes -15 -25 -33 units min max min max min max input clock frequency f ck 0 15 0 25.6 0 33 mhz fir clock frequency f fir 0 15 0 25.6 0 33 mhz input clock period t ck 66-39-30-ns fir clock period t fir 66-39-30-ns clock pulse width low t spwl 26-16-13-ns clock pulse width high t spwh 26-16-13-ns clock skew between fir_ck and ck_in t sk 0t fir -250t fir -150t fir -15 ns ck_in pulse width low t ch1l notes 5, 8 29 - 19 - 19 - ns ck_in pulse width high t ch1h notes 5, 8 29 - 19 - 19 - ns ck_in setup to fir_ck t cis notes 5, 8 27 - 17 - 17 - ns ck_in hold from fir_ck t cih notes 5, 8 2 -2-2-ns reset pulse width low t rspw 4t ck -4t ck -4t ck -ns recovery time on reset t rtrs 8t ck -8t ck -8t ck -ns ast ar tin pulse width low t ast t ck +10 - t ck +10 - t ck +10 - ns st ar t out delay from ck_in t stod -35-20-18ns st ar tin setup to ck_in t stic 25-15-10-ns setup time on data_in t set 20-15-14-ns hold time on all inputs t hold 0-0-0-ns write pulse width low t wl 26-15-12-ns write pulse width high t wh 26-20-18-ns setup time on address bus before the rising edge of write t stadd 26-20-20-ns setup time on chip select before the rising edge of write t stcs 26-20-20-ns setup time on control bus before the rising edge of write t stcb 26-20-20-ns data_rdy pulse width low t drpwl 2t fir -20-2t fir -10 - 2t fir -10 - ns data_out delay relative to fir_ck t firdv -50-35-28ns data rdy valid delay relative to fir_ck t firdr -35-25-20ns data_out delay relative to out_selh t out -25-20-20ns output enable to data out valid t oev note 6 - 15 - 15 - 15 ns output disable to data out three-state t oez note 5 - 15 - 15 - 15 ns output rise, output fall times t r , t f from 0.8v to 2v, note 5 -8-8-6ns notes: 5. controlled by design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. 6. transition is measured at 200mv from steady state voltage with loading as specified in test load circuit with and c l = 40pf. 7. ac testing is performed as follows: input levels (clk input) 4.0v and 0v, input levels (all other inputs) 0v and 3.0v, timing reference levels (clk) = 2.0v, (others) = 1.5v, output load per test load circuit and c l = 40pf. 8. applies only when h_byp = 1 or h_drate = 0. hsp43220
3-211 ac test load circuit note: test head capacitance. equivalent circuit c l (note) i oh 1.5v i ol dut switch s1 open for i ccsb and i ccop s 1 timing waveforms figure 16a. figure 16b. figure 16. input timing figure 17a. figure 17b. figure 17. start timing t set t hold clk_in data_in fir_ck t sk clk_in t fir t spwh t spwl t chil t chih t ck t ast ast ar tin ck_in ck_in t set t stod t stic st ar t out t hold data_in st ar tin t hold t wh c_bus ao-1 cs wr t stcb t stadd reset t rtrs t hold t hold t wl t rspw t stcs hsp43220
3-212 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 figure 18a. figure 18b. figure 18c. figure 18d. figure 18. timing waveforms (continued) fir_ck t firdr t firdr data_rdy current output previous output data_out t firdv t drpwl lower 8 bits upper 8 bits data_out 16-23 t out out_selh data_out 0-d23 t f 2.0v 0.8v t r data_out valid out_ enx out_ enp t oev t oez 1.7v 1.3v hsp43220

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